Testable Clock Routing Architecture for Field Programmable Gate Arrays
نویسندگان
چکیده
Abstract This paper describes an efficient methodology for testing dedicated clock lines in Field Programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. The Htree architecture provides optimal clock skew characteristics. The H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing schemes. A testing scheme, which utilizes the partial reconfiguration capabilities of FPGAs through selective re-programming of the Complex Logic Blocks, to detect and locate faults in the clock lines is proposed.
منابع مشابه
Design and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
متن کاملField Programmable Gate Array–based Implementation of an Improved Algorithm for Objects Distance Measurement (TECHNICAL NOTE)
In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost field programmable gate arrays from the Xilinx Spartan fami...
متن کاملFPGA Placement and Routing Algorithm: A Survey
Unlike ASICs, FPGAs have routing fabrics that are pre-manufactured. And because of this prefabrication, FPGAs hardly can achieve high clock frequencies which offered by ASICs. Thus, there is a need for better FPGA timing performance. And design automation or computer-aided design (CAD) tools for field programmable gate arrays (FPGAs) have played a very critical role over the past decades for FP...
متن کاملVON HERZEN : SIGNAL PROCESSING AT 250 MHz USING HIGH - PERFORMANCE FPGA
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250-MHz cross correlator for radio astronomy. Experimental results indicate that complementary metal–oxide–semiconductor (CMOS) field programmable gate arrays (FPGA’s) can perform useful computation at 250 MHz. The notion of an “event horizon” for FPGA’s leads to clear design cons...
متن کامل